Alafi Dumo

~/mini-container-runtime

Minimal Docker-like runtime built in Go with namespaces, cgroups and an OCI Registry client for pulling and running container images.

Go · Linux Namespaces (UTS, PID, MNT, USER) · cgroups v2 · OCI Registry API

githubdemo

~/weblate-contribution

Merged fix to Weblate, an open-source localization platform: diagnosed a time-of-check/time-of-use race in the Django REST API where a unit deleted mid-request returned an unhandled 500 instead of a 404, and added a deterministic regression test with no threads or sleeps. Shipped in release 2026.8.1.

Python · Django REST Framework · Concurrency · Open Source

github

~/memcached-cli-client

A Python command-line tool for interacting with Memcached, supporting core operations (set, get, add, replace, append, prepend) with protocol serialization over raw sockets.

Python · Pytest · Sockets · Memcached Protocol

githubdemo

~/nupython-interpreter

A lightweight Python interpreter written in C, using Backus-Naur Form grammar parsing for tokenization and execution, with dynamic memory allocation and a custom garbage collector hardened against malformed input.

C · Python · Google Test (GTest) · Garbage Collection

~/travel-scheduler

A C++ navigation tool over OpenStreetMap data for the Northwestern campus area. Parses OSM XML into an indexed node store, models buildings, bus stops, and amenities through a shared entity hierarchy, and queries the CTA Bus Tracker API for live arrival times with fallback handling when requests fail.

C++ · OpenStreetMap · CTA Bus Tracker API · libcurl · tinyxml2

~/ai-agent-stock-trading

DQN agent (reinforcement learning) that learns and optimises trading strategies, with a Streamlit dashboard for live visualisation and parameter tuning.

Python · Pandas/NumPy · Scikit-learn · Matplotlib · Streamlit

githubdemo

~/loan-recovery-risk-scoring

A machine-learning dashboard for borrower segmentation, high-risk prediction, and recovery strategy visualisation.

Python · Pandas · Plotly · Scikit-learn · Streamlit

githubdemo

~/async-fifo-sva

A dual-clock asynchronous FIFO in SystemVerilog using Gray-code pointer synchronization to pass data safely across independent clock domains. SystemVerilog Assertions enforce protocol compliance, asserting zero read-underflow or write-overflow under maximum strain, and a self-checking testbench reaches 100% functional coverage across empty, full, and near-boundary conditions.

SystemVerilog · SVA · Verilator · GTKWave · CDC

github

~/axi4-lite-interconnect

An AXI4-Lite crossbar interconnect in SystemVerilog supporting one master and two memory-mapped slave peripherals (UART and Timer). Handles backpressure, address decoding, and decoupled read/write channel handshakes per the ARM AXI4-Lite specification. Synthesized in Vivado for a Xilinx Artix-7 target, closing timing at 100 MHz.

SystemVerilog · Vivado · Verilator · AXI4-Lite · Xilinx Artix-7

github

~/riscv-pipelined-core

A 5-stage RV32I pipeline in SystemVerilog with dedicated hazard-detection and register forwarding units, resolving load-use stalls and branch flushes. Verified against bare-metal test suites at 1.18 CPI on Dhrystone, and synthesized for a Xilinx Artix-7 (XC7A35T) closing timing at 80 MHz using roughly 2,400 LUTs and 4 Block RAMs.

SystemVerilog · RV32I · Vivado · Verilator · Pipelining